1. Field of the Invention
The present invention relates to a switch circuit of a monolithic microwave integrated circuit (MMIC) device for controlling intermittence of an input signal, and more particularly to a switch circuit which has a depletion mode n-channel MOSFET (metal oxide semiconductor field effect transistor) which can be used in a circuit allowing only a positive voltage to be supplied therein.
2. Description of the Prior Art
In an MMIC allowing only a positive voltage to be supplied, an enhancement mode n-channel MOSFET must be used as a switch circuit for controlling intermittence of an input signal. It is well-known in this art that such an enhancement mode n-channel MOSFET is complicated in structure and is difficult in fabrication sequence thereof, as compared to a depletion mode MOSFET.
If a depletion mode n-channel MOSFET (hereinafter, referred to as "D-FET") is embodied in an MMIC, as a switch circuit, the MMIC stands in need of a negative voltage in addition to a positive voltage.
FIG. 1 is a circuit diagram of a prior art switch circuit which is constituted by a D-FET.
Referring to FIG. 1, the prior art switch circuit comprises a D-FET 101, a first bias resistor 102 connected between a drain of the D-FET 101 and a positive voltage source Vdd, a second bias resistor 103 connected between a source of the D-FET 101 and a ground, a bypass capacitor 104 connected in parallel with the second bias resistor 103 to bypass an RF (radio frequency) signal to the ground, a gate bias resistor 105 connected between the intermittence controlling voltage source Vc and a gate of the D-FET 101, and a third bias resistor 106 connected between the voltage source Vc and the ground. Also, in FIG. 1, reference characters "Sin" and "Sout" indicate input and output terminals, respectively.
In this switch circuit, an input signal is applied to the gate of the D-FET 101, and an output signal is obtained from the drain of the D-FET 101.
In the prior art switch circuit, if the intermittence controlling voltage Vc greater than a threshold voltage Vt of the D-FET 101 is applied therein, the D-FET 101 is operated as an amplification mode. However, if the voltage Vc less than the threshold voltage Vt thereof is applied therein, it is operated as a cut-off mode. The amplification mode means that the input signal is amplified by the D-FET 101 and outputted through the output terminal Sout, and the cut-off mode means that the input signal is not amplified by the D-FET and not outputted.
As described above, since the threshold voltage Vt of the D-FET 101 is a negative voltage, there arises the problem that the intermittence controlling voltage of a negative voltage is unavoidably required for such a switch circuit.